# NVRAM board text file for the BCM947189acnrm P104 March 10th, 2015
#
# Copyright 2011, Broadcom Corporation
# All Rights Reserved.
#
# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
# FOR A SPECIFIC PURPOSE OR NON-INFRINGEMENT CONCERNING THIS SOFTWARE.

# boardtype describes what type of Broadcom reference board that the design resembles
#   Reference Board  boardtype    Reference Board  boardtype
#   ---------------  ---------    ---------------  ---------
#     BCM94704agr     0x042F        BCM95356ssnr    0x0505
#     BCM94712ap      0x0445        BCM94718nrl     0x050D
#     BCM94712p       0x0446        BCM94718nrx     0x050E
#     BCM94712agr     0x0451        BCM947186nrh    0x052A
#     BCM95350gr      0x0456        BCM947186nr2    0x052B
#     BCM94712lgr     0x0460        BCM94718nrlfmc  0x052C
#     BCM95352gr      0x0467        BCM95357nr      0x053A
#     BCM95351agr     0x0470        BCM95357nrepa   0x053B
#     BCM94704mpcb    0x0472        BCM95358nr2     0x053D
#     BCM94712agsdio  0x047B        BCM95357nr2epa  0x054C
#     BCM95352elgr    0x047F        BCM95357nr2     0x054D
#     BCM94705lmp     0x0489        BCM95357cbtnr2epa 0x056A
#     BCM94705gmp     0x0489        BCM94706nr      0x05B2
#     BCM94705gmp115  0x0489        BCM94706nrh     0x05D8
#     BCM94312mcg     0x048B        BCM947189acnrm  0x0782 
#     BCM94312mcag    0x048C
#     BCM95354gr      0x048E
#     BCM94705nogig   0x0496
#     BCM94703nr      0x04C0
#     BCM94716nr2     0x04CD
#     BCM94717ap      0x04CE
#     BCM94718nr      0x04CF
#     BCM94717mii     0x04ED
#     BCM94717cbtnr   0x04EF
#     BCM94716nr2ipa  0x04FB
#
# set a boardtype of BCM947189acnrm
boardtype=0x0782

# boardnum is set by the nvserial program. Don't edit it here.
boardnum=${serno}

# Board revision.
# With sromrev 4 and above, the boardrev is a 16 bit number as follows:
# Bits [15:12] - Board Revision Type (brt), a 4 bit number with values:
#                0: Legacy (old boardrev numbering scheme)
#                1: Prototype "P" board.
#                2: Production "A" board.
#                3-15: Reserved.
# Bits [11:0] - Board revision, 12 bits which use BCD encoding to represent a decimal number between 0 and 999.
#
# Ex: A legacy board rev of 4.5 is 0x0045
# Ex: A P304 board rev is 0x1304
#
# Board revision is P101
boardrev=0x1104

# boardflags: 32-bits (LSB on top, MSB on bottom)
#   0 = no Bluetooth coexistence                                 1 = board supports Bluetooth coexistence
#   0 = This board doesn't have gpio 9 controlling the PA        1 = This board has gpio 9 controlling the PA
#   0 = does not implement GPIO 13 radio disable (Airline mode)  1 = board implements Airline mode on GPIO 13
#   0 = This board doesn't have the rssi ADC divider             1 = This board has the rssi ADC divider
#  ---
#   0 = board does not have RoboSwitch or Ethernet switch core   1 = has RoboSwitch chip or Ethernet switch core
#   0 = OK to power down PLL and oscillator                      1 = Not ok to power down pll and oscillator
#   0 = no high power CCK (disables opo parameter)               1 = can do high power CCK transmission (enables opo)
#   0 = board does not have ADMtek switch                        1 = board has ADMtek Ethernet switch
#  ---
#   0 = Ethernet switch does not have VLAN capability            1 = Ethernet switch has VLAN capability
#   0 = LTE Coex disabled                                        1 = LTE Coex enabled
#   0 = chip has it's PCI/PCIe interface connected               1 = PCI/PCIe is floating or there is no PCI/PCIe interface on the chip
#   0 = board does not have a FEM                                1 = board uses a FEM
#       (legacy SISO chips only, not used for MIMO chips)
#  ---
#   0 = board does not have an external 2.4GHz LNA               1 = board has an external 2.4GHz LNA
#   0 = board does not have a high gain PA                       1 = board has a high gain PA
#       (legacy SISO chips only, not used for MIMO chips)
#   0 = no alternate Bluetooth coexistence                       1 = 2-wire BT coex on GPIOs 4 & 5
#   0 = do not use alternate IQ imbalance settings               1 = use alt IQ settings
#       (only applies to 4318)
#  ---
#   0 = board has external PA(s)                                 1 = board does not have external PA(s)
#       (legacy SISO chips only, not used for MIMO chips)
#   0 = board's TSSI is negative slope                           1 = board's TSSI is positive slope
#       (legacy SISO chips only, not used for MIMO chips)
#   0 = board does not use the PA voltage reference LDO          1 = board uses the PA voltage reference LDO
#       (only applies to the 4326, 4328, and 5354)
#   0 = no triple-throw switch shared with Bluetooth             1 = has triple-throw switch shared with BT
#  ---
#   0 = chip does not support the phase shifter for MRC          1 = chip supports the phase shifter for MRC
#       (applies to 4325, 4326, 4328, and 5354 only)
#   0 = board power topology does not use the Buck/Boost reg     1 = board power topology uses the Buck/Boost regulator
#       (4325 only)
#   0 = board does not share antenna with Bluetooth              1 = board has FEM and switch to share antenna with BT
#   0 = board power topology uses CBUCK (core buck)              1 = board power topology does not use CBUCK (core buck)
#       (applies to 4325 only)
#  ---
#   0 = normal CCK EVM and spectral mask                         1 = favor CCK EVM over spectral mask
#   0 = board power topology does not use PALDO                  1 = board power topology use PALDO
#   0 = normal LNLDO2 (low noise LDO2)                           1 = select 2.5V as LNLDO2 (low noise LDO2) output voltage
#       (4325 only)
#   0 = non 4325: no minimum power index                         1 = non 4325: enforce minimum power index to avoid FEM damage
#       (set to "1" only for SiGe SE2559L FEMs)
#       4325: no power-on-reset workaround                           4325: Apply power-on-reset workaround
#  ---
#   0 = board does not have an external 5GHz LNA                 1 = board has an external 5GHz LNA
#   0 = for a 1x2 design, board does not have two T/R switches   1 = for a 1x2 design, board has two T/R switches
#   0 = normal operation of 5GHz T/R switch for high RF          1 = hold T/R switch in the "R" position for high RF input powers.
#       input power.
#   0 = use normal "InitGain"                                    1 = backoff "InitGain" based on the elna2g/5g parameters, for external LNAs only.
#
boardflags=0x10000110

# boardflags2: 32-bits (LSB on top, MSB on bottom)
#   0 = board uses the 2055's built-in LDOs to power the 2055    1 = board uses external rxbb regulator to power the 2055
#   0 = use normal 5GHz band PLL settings                        1 = use alternate 5GHz band PLL settings
#       (4322x and 4716/17/18 only)
#   0 = do not use H/W TX power control on 4321                  1 = use H/W TX power control on 4321
#       (4321 only)
#   0 = board does not support the 2x4 diversity switch          1 = board supports the 2x4 diversity switch
#  ---
#   0 = board does not support the 5GHz band TX power gain       1 = board supports the 5GHz band TX power gain
#   0 = board does not override the ASPM and CLKREQ settings     1 = board overrides the ASPM and CLKREQ settings
#   0 = board is not a BCM94321mc123 board                       1 = board is a BCM94321mc123 board (unused by S/W)
#   0 = board uses SECI Bluetooth coexistence                    1 = board uses 3-wire Bluetooth coexistence
#  ---
#   0 = BCM94321mcm93 uses SiGe FEM                              1 = BCM94321mcm93 uses Skyworks FEM
#       (for BCM94321mcm93 and BCM94321coex boards only)
#   0 = no workaround for clock harmonic spurs                   1 = use the workaround for clock-harmonic spurs
#   0 = use normal 2.4GHz band PLL settings                      1 = use alternate 2.4GHz band PLL settings
#       (4322x and 4716/17/18 only)
#   0 = Normal LED drive (full push-pull)                        1 = Drive the LED outputs as open-drain
#       (43224 only)
#  ---
#   0 = enable TX diversity for 11b frames                       1 = Transmit 11b frames only on antenna 0
#   0 = no WAR to reduce/avoid clock harmonic spurs in 2G band   1 = enable WAR to reduce/avoid clock harmonic spurs in 2G band
#   0 = do not transmit 11b frames using all TX cores            1 = transmit 11b frames using all TX cores
#       (TX diversity enabled or not by bit 12)                      (no TX diversity)
#   0 = use normal filter settings for 2.4GHz bandedge channels  1 = use alternate filter settings for 2.4GHz bandedge channels
#       (4716, 4717, 4718, 5357, 5358, and 47186 internal PAs only)
#  ---
#   0 = do not use 200kHz PLL bandwidth for 2G band              1 = use 200kHz PLL bandwidth for 2G band
#   0 = GPAIO pin is not connected to 3.3V                       1 = GPAIO pin is connected to 3.3V
#       (43226 only)
#   0 = for external PAs, use external TSSI for TX IQCAL         1 = use internal envelope detector for TX IQCAL even with external PAs
#       (4322x and 4716/17/18 only)
#   0 = can turn off the buffered crystal output from the radio  1 = keep the buffered crystal output from radio ON
#  ---
#   0 = control 2GHz PAs with the digital PA control signals     1 = control 2GHz PAs with the analog PA VERF LDO outputs
#   0 = control 5GHz PAs with the digital PA control signals     1 = control 5GHz PAs with the analog PA VERF LDO outputs
#   0 = normal external LNA and TR switch controls               1 = For AZW designs, 2GHz gmode_elna_gain conrols the TR switch
#       (4329 only)
#   0 = no antenna sharing with Bluetooth                        1 = share the chain 0 antenna with Bluetooth
#  ---
#   0 = no adjustment to the temperature threshold, "tempthresh" 1 = chip can sustain a higher tempsense threshold
#                                                                    add the value of parameter "tempoffset" to "tempthresh"
#   0 = use standard 4-wire Bluetooth coexistance                1 = use standard 3-wire Bluetooth coexistance only. 4-wire not supported
#   0 = 4331 power savings mode enabled (use for STAs)           1 = 4331 power savings mode disabled (use for routers)
#       (4331 only)
#   0 = no ucode powersave WAR                                   1 = enable ucade powersave WAR
#       (4331 only)
#  ---
#   0 = enable dynamic Vmid in idle TSSI calibration             1 = disable dynamic Vmid in idle TSSI calibration
#   0 = SDR disabled                                             1 = SDR enabled
#   0 = acphy, disable lna1 bypass for clip gain, 2g						 1 = acphy, enable lna1 bypass for clip gain, 2g
#   0 = acphy, disable lna1 bypass for clip gain, 5g						 1 = acphy, enable lna1 bypass for clip gain, 5g
boardflags2=0xc0000000

# boardflags3: 32-bits (LSB on top, MSB on bottom)
#   bits 0-2: (AC PHY only) subrevisions on femctrl on top of normal femctrl
#   000 = 53573acnr 5G ref board                                 001 = 53573acr bu board with low cost dual band fem
#   010 = 2	47189 bu board with dual band fem(epa elna)          011 = 47189 ref board 5G only fem(epa elna)
#
#   bit 3: rcal war active on this board (mainly for 4335a0)
#   0 = disable                                                  1 = enable
#  ---
#   bits 6-4: (AC PHY only) txgain table id, set as 0 by default
#
#   0 = disable	20 vs 40 vs 80 TSSI divergence WAR               1 = enable 20 vs 40 vs 80 TSSI divergence WAR
#  ---
#   0 = femctrl table is not read from nvram                     1 = femctrl table is read from nvram
#   0 = disable AGC configuration for 2G                         1 = enable AGC configuration for 2G
#   0 = disable AGC configuration for 5G                         1 = enable AGC configuration for 5G
#   0 = disable ppr bit extension																 1 = enable ppr bit extension
#   sb40and80hr5glpo bits[15:4], sb40and80hr5gmpo bits[9:4] and sb40and80hr5ghpo bits[9:4]
#  ---
#   0 = enable bbpll spur modes 																 1 = disable bbpll spur modes
#   0 = disable to read rcal_trim value from otp                 1 = enable to read rcal_trim value from otp
#   0 = do not blank the first X ticks of 2g gaintbl             1 = blank the first X ticks of 2g gaintbl
#   0 = do not blank the first X ticks of 5g gaintbl             1 = blank the first X ticks of 5g gaintbl
#  ---
#   bits 18-16: unsed in this chip
#   0 = disable spur WAR in 5G band                              1 = enable spur WAR in 5G band
#  ---
#   bits 21-20: for lpmode_2g choice
#   bits 23-22: for lpmode_5g choice
#  ---
#   bits 25-24: unused
#   0 = Do not force internal lpo                              1 = Force internal lpo
#   0 = Do not force external lpo                              1 = Force external lpo
#  ---
#   0 = Do not Allow BRCM Implicit TxBF                          1 = Allow BRCM Implicit TxBF
#   0 = -                                                        1 = - 
#   0 = Disable to Read Av Vmid from NVRAM                       1 = Enable to Read Av Vmid from NVRAM
#   0 = Do not read Vlin En from NVRAM                           1 = Read Vlin En from NVRAM
boardflags3=0x40500182

# bootflags
#   0 = NOR boot only                                            1 = NOR boot + kernel on NAND
bootflags=0

# sromrev tells the software what "version" of NVRAM is used. This is just for the CPU chip. The wireless chips will
# their own sromrev settings.
sromrev=11


# For BCM47189: ARM clock frequency in MHz, DDR clock freq in MHz.
# See table in source code file /src/shared/hndmips.c or /src/shared/hndarm.c for the valid clkfreq settings for a given chip.
#
clkfreq=900,533

# frequency of the crystal driving the PLL, in kHz
# Even if the chip does not support any other crystal frequency, this parameter must still be specified.
xtalfreq=40000

# SDRAM Memory Configuration Parameters

# For the BCM47189:
#
# Bits   Definition
# -----  -----------------------------------------------------------------------------------------------------------
# 15:11  Reserved
#  10:8  Column Size: 000 = 2048 columns; 001 = 1024 columns; 010 = 512 columns
#   7    0 = 32 bit wide data bus; 1 = 16 bit wide data bus
#   6    0 = 4 banks; 1 = 8 banks
#            NOTE: For 4 banks, columns can be 512, 1024, or 2048. For 8 banks, columns can only be 1024 or 2048.
#  5:3   Reserved
#  2:0   CAS latency: 011 = CL is 3; 100 = CL is 4; 101 = CL is 5; 110 = CL is 6; 111 = CL is 7; all others reserved
#
# Set 256MB (2Gbit) of DDR3 (DDR3 64MX16), x32, 8 banks, CL=7
sdram_config=0x0147

# Not defined yet
# sdram_ncdl=0
# sdram_refresh=0x81c

# Configure the RGMII port to talk to the external Ethernet switch (RoboSwitch)
# et0phyaddr is the PHY address of the PHY chip or the address of the RGMII port of the switch chip.
et0phyaddr=30
# et0mcdport is which MDC/MDIO port is used to connect to the PHY/Switch chip. Only 47189 has two RGMIIs, so this
# parameter is nearly always "0".
et0mdcport=0

# Set the MAC address of the Ethernet ports
# Up until 9/2009 MAC addresses had the format:
#   47   40 39   32 31   24 23   16 15    8 7     0
#  |  00   |  90   |  4C   |  XX   |  YY   |  YY   |
# where YYYY is the serial number and XX was assigned per interface and per boardtype. The macmid covered bits 31:16
# which includes the 0x4C octet from the OUI and the XX value. That allowed 65536 serial numbers for each board type
# but only 256 distinct interface/ boardtype combos.
#
# From 9/2009 onward MAC addresses have changed from that 8/16 split to a 12/12 split, so the new macmid will be
# based on MAC addresses with the following format:
#   47   40 39   32 31   24 23   16 15    8 7     0
#  |  00   |  90   |  4C   |  XX   |  XY   |  YY   |
# where the low 24 bits are evenly split into 4096 interface/ boardtypes and 4096 serial numbers. The low nibble of
# XXX cannot be 0, since that corresponds to an old style MAC address, and macmid will correspond to bits 23:12, so
# its easy to differentiate them from the old ones.
#
# The new "macmid" values will start at 1 and go up to 0xFFF, skipping those that have the low nibble as 0 and the
# ones with the patterns 0x04Ex and 0x04Fx (These restrictions are enforced in the code). To form the mac address,
# the whole OUI (00:90:4C) will be prepended to those values and 12 bits of serial number will be appended.
#
# An old-style macmid:
#   BCM94716nr2   0x4C04
# a new-style macmid:
#   BCM947186nrh  0x008
#
# For router boards, nvserial now defines a new variable: "maclo12"
# so nvram text files for new boards will have to define the MAC address like this (for a macmid 0x008):
#   et0macaddr=00:90:4C:00:8${maclo12}
# instead of the previous way:
#   et0macaddr=00:90:4C:FC:${maclo}
#
# Set the MAC address of the Ethernet ports
#   Reference Board   macmid
#   ---------------  ---------
#     BCM94704agr      4C:4E (1st MII)
#     BCM94704agr      4C:4F (2nd MII)
#     BCM94712ap       4C:68
#     BCM94712agr      4C:76
#     BCM95350gr       4C:7D
#     BCM94712lgr      4C:88
#     BCM95352gr       4C:91
#     BCM95352grl      4C:91
#     BCM95351agr      4C:9C
#     BCM94704mpcb     4C:A0 (1st MII)
#     BCM94704mpcb     4C:A1 (2nd MII)
#     BCM94704nr       4C:A0 (1st MII)
#     BCM94704nr       4C:A1 (2nd MII)
#     BCM95352elgr     4C:AD
#     BCM94705gmp      4C:B9
#     BCM95354gr       4C:C0
#     BCM94703nr       4C:F0 (1st MII)
#     BCM94703nr       4C:F1 (2nd MII)
#     BCM94716nr2      4C:04
#     BCM94717ap       4C:06
#     BCM94718nr       4C:08
#     BCM94717mii      4C:2D
#     BCM94717cbtnr    4C:2F
#     BCM95356ssnr     4C:36
#     BCM94718nrl      4C:56
#     BCM94718nrx      4C:57
#     BCM947186nrh     00:8
#     BCM95357nr       01:2
#     BCM95357nrepa    01:4
#     BCM95358nr2      01:6
#     BCM947186nr2     01:E
#     BCM95357nr2epa   01:4
#     BCM95357cbtnr2epa 02:8
#     BCM94718nrlfmc   05:6
#     BCM94706nr       08:A
#     BCM94706nrh      0B:4
#     BCM947189acnrm   1E:2
#     BCM47189acnrh    1E:5
#
# The value of 00:90:4C:1E:2 is for a BCM947189acnrm reference design.
# The "maclo12" part is filled in by the nvserial program.
et0macaddr=00:90:4C:1E:2${maclo12}

# Ethernet switch VLAN configuration.
# These parameters configure VLANs (Virtual LANs) for the internal or external Ethernet switch. This is done mainly
# to separate the WAN port of a router from the LAN ports.
# All Broadcom switches that have MAC ports with built-in PHYs will number the ports with PHYs starting at 0 and
# incrementing upwards. For the MAC ports without PHYs, the numbering of that port(s) can vary. The table below shows
# the numbering of the MAC only ports in various Broadcom chips.
#
#  Broadcom Chip   MAC only ports
#  --------------  --------------
#  BCM5356               5
#  BCM5357/5358U         5
#  BCM5358               5
#  BCM47186              8
#  BCM53115             5,8
#  BCM53125             5,8
#  BCM4707/8/9/81      5,7,8
#
# One of these ports will connect the Ethernet switch to the CPU of the wireless chip. For chips will built-in Ethernet
# switches and PHYs, this port will be internal to the chip. This port number must be included in every VLAN definition
# for the wireless chip to be able to route/bridge network traffic between the Ethernet ports, the wireless network(s),
# and any other network device in the design (such as DSL, PLC, cellular data, etc?.
#
# A special symbol - an "*" - must be added to the end one, and only one, vlanXports parameter. This indicates which
# VLAN is to be used by the bootloader for Ethernet network connections. Typically this the VLAN for the LAN ports.
#
# There are two other special tags that can be added after the MAC port number that connects to the CPU:
#   "u" - configures the switch to not add VLAN tags for packets to/from the CPU and the other port(s) in the VLAN port list.
#   "t" - configures the switch to add VLAN tags for packets to/from the CPU and the other port(s) in the VLAN port list.
#         This is the normal behavior so the "t" is usually omitted.
#
# Also see the note under "wandevs" parameter when the WAN VLAN is tagged.
# Typically vlan1 is the LAN, and vlan2 is the WAN)
# NOTE: Bit 8 of boardflags must be set to "1" for these parameters to work.
#
# WAN is on port 0, LAN is on ports 1-4. 
# "8" for the BCM53125 RGMII(IMP) port number.
# "5" for the BCM53125 RGMII(Port 5) port number 
## vlan1 is the LAN.

vlan1ports=1 2 3 4 8*
vlan1hwname=et0

# vlan2 is the WAN. The "u" configures the switch to not add vlan tags for packets to/from the
# WAN port. A "t" (or nothing) in place of the "u" will configure the switch to add vlan tags for packets
# to/from the WAN port. Also see note under "wandevs".
#vlan2ports=0 8u
vlan2ports=0 8
vlan2hwname=et0

# If the board is a dual band design the second wireless interface (usually the "a" band)
# will come up as a second device. But we have to tell the software to hook to this
# second wireless interface named  "wl1". So set "landevs=vlan1 wl0 wl1".
landevs=vlan1 wl0 wl1

# The WAN port is almost always on an Ethernet port so use the normal config. If the WAN
# port is not an Ethernet port, then this parameter must be changed accordingly.
# NOTE: If WAN packets are vlan tagged, then must use "vlan2" in place of "et0".
#       For the default case of no WAN vlan tags, then must use "et0".
# NOTE: If the board does not have a WAN port then must use "wandevs=".
# WAN port is on eth0.
wandevs=et0

# Set default IP address and net mask for the router.
lan_ipaddr=192.168.1.1
lan_netmask=255.255.255.0

# If the board supports WPS, then these parameters tell the software
# which GPIO is used for the WPS pushbutton and which is used for the WPS LED indicator.
gpio10=wps_led
gpio9=wps_button

# Set a short delay on boot so the CFE delays a bit before loading Linux. Allows easier S/W updates.
boot_wait=on
# If boot_wait is on, then "wait_time" sets the wait time from 3 to 20 seconds.
wait_time=3

# The reset button is on GPIO 5. It MUST be active low, or the software will have to be modified.
reset_gpio=7

# If the board has an external Ethernet switch then the reset line to the
# switch is controlled with a GPIO from the CPU chip. This is set with the
# parameter "gpioX=robo_reset". Where X is the GPIO number, 0-31.
gpio2=robo_reset

# If the board has a USB power control chip, then the parameter "gpioX=usbportY" is used to tell
# the USB driver code that it needs to set that GPIO HIGH to turn on power to that USB port.
# "X" is the GPIO number, 0-31. "Y" is the USB port number, starting at "1".
gpio8=usbport1

# Watchdog timer in ms (0 will disable), 3000ms is minimum. 5592ms is maximum.
watchdog=3000

# defined GPIO4 for the watchdog reset bug on A0 chip
gpio4=watchdog_reset_gpio

# defined GPIO13 for the PCIe reset bug on A0 chip
gpio13=pcie_reset

# Wombo rest for 43217
#gpio12=wombo_reset

# The i2c_sda_gpio and i2c_scl_gpio tell the audio driver which GPIOs are used for the I2C SDA and SCL signals.
# The I2C bus is "bit-banged" in software and is used to configure the audio codec.
# These parameters only have effect when the audio driver is included in the router/AP software build.
#i2c_sda_gpio=22
#i2c_scl_gpio=21


# For simultaneous dual band designs where one of the wireless interfaces is also on the same chip
# as the CPU, then we have to prefix all those wireless parameters with "sb/1/". Also, the parameters
# such as boardflags, boardflags2, and sromrev must be present with the "sb/1/" prefix and be the same
# as the non-prefixed versions above.

# venid is the "vendor ID" of the wireless chip. 0x14E4 is Broadcom (Epigram)
# sb/1/venid=0x14E4

# sromrev tells the software what "version" of SROM is used.
sb/1/sromrev=11

# The same as "boardflags"
sb/1/boardflags=0x10000110

# The same as "boardflags2"
sb/1/boardflags2=0xc0000000

# The same as "boardflags3"
sb/1/boardflags3=0x40500182

#Refer to subrevisions on femctrl is 3(on the boardflags3 bits[2:0]), here are the mapped value for the switch control map from the system
#Please do not change and it will be defined by the system
sb/1/swctrlmap_2g=0x00000808,0x30300000,0x10100000,0x000000,0x3ff
sb/1/swctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000
sb/1/swctrlmap_5g=0x00000101,0x06060000,0x02020000,0x000000,0x3ff
sb/1/swctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000

# This parameter will tell the software to hook to the external wireless chip's d11 wireless core
# and tell it what type of wireless interface this is.
#
#   wireless interface type  chips                         device ID
#   -----------------------  ----------------------------  ---------
#   Dual band 11ac           4360                            0x43A0
#   2.4GHz only 11n          4360                            0x43A1
#   5GHz only 11ac           4360                            0x43A2
#   2.4GHz only 11n          43217                           0x43A9
#   2.4GHz only 11n          43131                           0x43AA
#   Dual band 11ac           4335                            0x43AE
#   2.4GHz only 11n          4335                            0x43AF
#   5GHz only 11ac           4335                            0x43B0
#   Dual band 11ac           4352                            0x43B1
#   2.4GHz only 11n          4352                            0x43B2
#   5GHz only 11ac           4352                            0x43B3
#   Dual band 11ac           53573                           0x43B4
#   2.4GHz only 11n          53573                           0x43B5
#   5GHz only 11ac           53573                           0x43B6 
#   Dual band 11ac           47189                           0x43C6
#   2.4GHz only 11n          47189                           0x43C7
#   5GHz only 11ac           47189                           0x43C8
sb/1/devid=0x43C8

# sb/1/macaddr sets the MAC address of the WOMBO 11n wireless interface.  See notes above for et0macaddr for the new macmid definition.
sb/1/macaddr=00:90:4C:1E:3${maclo12}

# sb/1/aa2g sets which antennas are available for 2.4GHz. Value is a bit field:
# Bit 0 = 1 for antenna 0 is available, 0 for not.
# Bit 1 = 1 for antenna 1 is available, 0 for not.
# Bit 2 = 1 for antenna 2 is available, 0 for not.
# Bit 3 = 1 for antenna 3 is available, 0 for not.
sb/1/aa2g=0

# sb/1/aa5g sets which antennas are available for 5GHz. Value is a bit field:
# Bit 0 = 1 for antenna 0 is available, 0 for not.
# Bit 1 = 1 for antenna 1 is available, 0 for not.
# Bit 2 = 1 for antenna 2 is available, 0 for not.
# Bit 3 = 1 for antenna 3 is available, 0 for not.
# the board has two 5GHz antennas available
sb/1/aa5g=3

# agaX sets the antenna gain for the 5GHz antennas. Where X is 0-2, represeting antennas 0-2.
# Lower 6 bits are interpreted as a signed number representing whole dB.
# High 2 bits represent number of quarter dBs. qdB's are ALWAYS POSITIVE and are
# added to whole dBs, so -1 whole dB and 1 qdB = 0x7F = -1dB + 0.25dB = -0.75dB. Range is
# -32dB to +31.75 dB.
# set 0dB gain for all available 5GHz antennas
sb/1/aga0=0
sb/1/aga1=0
sb/1/aga2=0

# txchain is a bit field that sets how many TX chains are implemented.
# Bit 0 = 1 for TX chain 0 is implemented, 0 for not.
# Bit 1 = 1 for TX chain 1 is implemented, 0 for not.
# Bit 2 = 1 for TX chain 2 is implemented, 0 for not.
# Bit 3 = 1 for TX chain 3 is implemented, 0 for not.
# 47189 chip has TX chains 0 and 1
sb/1/txchain=3

# rxchain is a bit field that sets how many RX chains are implemented.
# Bit 0 = 1 for RX chain 0 is implemented, 0 for not.
# Bit 1 = 1 for RX chain 1 is implemented, 0 for not.
# Bit 2 = 1 for RX chain 2 is implemented, 0 for not.
# Bit 3 = 1 for RX chain 3 is implemented, 0 for not.
# 47189 chip has RX chains 0 and 1
sb/1/rxchain=3

# antswitch sets the type of antenna diversity switch used on the board
# 0 = no antenna diversity switch, not 2-of-3
# 1 = antenna diversity switch config as on BCM94321cb2 2of3
# 2 = antenna diversity switch config as on BCM94321mp 2of3
# 3 = antenna diversity switch config as on any 2of3 design newer than 4321
sb/1/antswitch=0

# femctrl is unsed by default, so set it as 15 (which FEM control LUT to use? index? 5-bits)
sb/1/femctrl=15

# subband5gver sets how the 5GHz band is divided up for purposes of max RF power settings
# and the PA parameter settings. There are currently only four valid different sub-band
# definitions: (all others reserved)
#
# 0: Three sub-bands for normal power PAs:
#
#    Subband   Frequency range  Channel Range
#    --------  ---------------  -------------
#    Low        5180 to 5320       36-64
#    Mid        5500 to 5700      100-140
#    High       5745 to 5825      149-165
#
# sb/1/ Three sub-bands for high power PAs:
#
#    Subband   Frequency range  Channel Range
#    --------  ---------------  -------------
#    Low        5180 to 5240       36-48
#    Mid        5260 to 5700       52-140
#    High       5745 to 5825      149-165
#
# 4: Four sub-bands for high power PAs: (only available in sromrev=9 or above)
#
#    Subband   Frequency range  Channel Range
#    --------  ---------------  -------------
#    Low        5180 to 5240       36-48
#    Mid        5260 to 5320       52-64
#    High       5500 to 5700      100-140
#    X1         5745 to 5825      149-165
#
# 7: Normal three sub-bands: (default)
#
#    Subband   Frequency range  Channel Range
#    --------  ---------------  -------------
#    Low        4905 to 5080      184-216
#    Mid        5180 to 5320       36-64
#    High       5500 to 5825      100-165
#
# Set the 4 sub-band definition.
sb/1/subband5gver=4

# For normal operation, init gain & clip gains & clip thresholds are derived from the elna & trloss parameters. If for
# some reason, any special gainctrl handling is needed, use these spare bits.
# Current not used for any board. Do NOT change the value of this parameter unless directed to by Broadcom!
# gainctrlsph is a 5 bit number.
sb/1/gainctrlsph=0

# papdcap5g indicates if the 5GHz RF front end has PAPD capability, 0=no, 1=yes
sb/1/papdcap5g=0

# tworangetssi5g is ??? (Enable two range TSSI for 5GHz? 1-bit)
sb/1/tworangetssi5g=0

# pdgain5g is ??? (power detector gain 5GHz? 3-bits)
sb/1/pdgain5g=0

# epagain5g is ??? (3-bits) (old def: sets what type of external 5GHz PA is used: 0 = full gain PA,  1 = PA "lite",  2 = no external PA, 3 = high power external PA)
sb/1/epagain5g=0

# tssiposslope5g sets the slope for the 5GHz TSSI to be either 0=negative or 1=positive
# set positive slope
sb/1/tssiposslope5g=1

# avvmid 
sb/1/AvVmid_c0=2,135,2,135,2,135,2,135,2,135
sb/1/AvVmid_c1=2,145,2,145,2,145,2,145,2,145

#paparam bw version
sb/1/paparambwver=3
paparambwver=3 

# pdoffset5gsubbanda0/1 are the offsets for 5GHz 20in40 and 20in80 subbands
# Each number is a 16-bit wide field that is broken up into four 4-bit offsets, one for each sub-band of 0-3.
# Sub-band 3 (X1) is in bits [15:12], sub-band 2 (high) in bits [1sb/1/8], sub-band 1 (mid) in bits [7:4], and sub-band 0 (low) in bits [3:0]
# Each offset is stored in twos compliment format. Units are 1/4 dB.
# Ex: 0x00A0 = -1.5dB offset for sub-band 1, that is 1.5dB is subtraced from the measured power to get the correct measured power.
sb/1/pdoffset5gsubbanda0=0x0000
sb/1/pdoffset5gsubbanda1=0x0000

# 5GHz RX Gain Parameteters

# rxgains5gelnagaina0 defines the external LNA gain for 5GHz, low sub-band, chain 0. Range: 0 - 7
# actual ext LNA gain = (rxgains5gelnagaina0 * 2) + 6, dB
# LNA gain is 12dB
sb/1/rxgains5gelnagaina0=3

# rxgains5gtrelnabypa0 is a boolean which states if an LNA bypass switch is used for 5GHz, low sub-band, chain 0.
# 0 = no LNA bypass swtich (LNA does not have a bypass path)
# 1 = LNA bypass switch is used (LNA has a bypass path)
sb/1/rxgains5gtrelnabypa0=1

# rxgains5gtrisoa0 defines the external isolation between Rx and Tx, for 5GHz, low sub-band, chain 0. Range: 0 - 15
# It is set according to two different equations, depending upon whether the LNA has a bypass path or not:
#   LNA does not have a bypass path: change in RX gain bettwen R and T = (rxgains5gtrisoa0 * 2) + 8, dB
#   LNA does have a bypass path: rxgains5gtrisoa0 = external LNA gain + LNA bypass loss
sb/1/rxgains5gtrisoa0=5

# rxgains5gmelnagaina0 defines the external LNA gain for 5GHz, mid sub-band, chain 0. Range: 0 - 7
# actual ext LNA gain = (rxgains5gelnagaina0 * 2) + 6, dB
# LNA gain is 12dB
sb/1/rxgains5gmelnagaina0=3

# rxgains5gmtrelnabypa0 is a boolean which states if an LNA bypass switch is used for 5GHz, mid sub-band, chain 0.
# 0 = no LNA bypass swtich (LNA does not have a bypass path)
# 1 = LNA bypass switch is used (LNA has a bypass path)
sb/1/rxgains5gmtrelnabypa0=1

# rxgains5gmtrisoa0 defines the external isolation between Rx and Tx, for 5GHz, mid sub-band, chain 0. Range: 0 - 15
# It is set according to two different equations, depending upon whether the LNA has a bypass path or not:
#   LNA does not have a bypass path: change in RX gain bettwen R and T = (rxgains5gtrisoa0 * 2) + 8, dB
#   LNA does have a bypass path: rxgains5gtrisoa0 = external LNA gain + LNA bypass loss
sb/1/rxgains5gmtrisoa0=5

# rxgains5ghelnagaina0 defines the external LNA gain for 5GHz, high and X1 sub-bands, chain 0. Range: 0 - 7
# actual ext LNA gain = (rxgains5gelnagaina0 * 2) + 6, dB
# LNA gain is 12dB
sb/1/rxgains5ghelnagaina0=3

# rxgains5ghtrelnabypa0 is a boolean which states if an LNA bypass switch is used for 5GHz, high and X1 sub-bands, chain 0.
# 0 = no LNA bypass swtich (LNA does not have a bypass path)
# 1 = LNA bypass switch is used (LNA has a bypass path)
sb/1/rxgains5ghtrelnabypa0=1

# rxgains5ghtrisoa0 defines the external isolation between Rx and Tx, for 5GHz, high and X1 sub-bands, chain 0. Range: 0 - 15
# It is set according to two different equations, depending upon whether the LNA has a bypass path or not:
#   LNA does not have a bypass path: change in RX gain bettwen R and T = (rxgains5gtrisoa0 * 2) + 8, dB
#   LNA does have a bypass path: rxgains5gtrisoa0 = external LNA gain + LNA bypass loss
sb/1/rxgains5ghtrisoa0=5

# rxgains5gelnagaina1 defines the external LNA gain for 5GHz, low sub-band, chain 1. Range: 0 - 7
# actual ext LNA gain = (rxgains5gelnagaina1 * 2) + 6, dB
# LNA gain is 12dB
sb/1/rxgains5gelnagaina1=3

# rxgains5gtrelnabypa1 is a boolean which states if an LNA bypass switch is used for 5GHz, low sub-band, chain 1.
# 0 = no LNA bypass swtich (LNA does not have a bypass path)
# 1 = LNA bypass switch is used (LNA has a bypass path)
sb/1/rxgains5gtrelnabypa1=1

# rxgains5gtrisoa1 defines the external isolation between Rx and Tx, for 5GHz, low sub-band, chain 1. Range: 0 - 15
# It is set according to two different equations, depending upon whether the LNA has a bypass path or not:
#   LNA does not have a bypass path: change in RX gain bettwen R and T = (rxgains5gtrisoa1 * 2) + 8, dB
#   LNA does have a bypass path: rxgains5gtrisoa1 = external LNA gain + LNA bypass loss
sb/1/rxgains5gtrisoa1=5

# rxgains5gmelnagaina1 defines the external LNA gain for 5GHz, mid sub-band, chain 1. Range: 0 - 7
# actual ext LNA gain = (rxgains5gelnagaina1 * 2) + 6, dB
# LNA gain is 12dB
sb/1/rxgains5gmelnagaina1=3

# rxgains5gmtrelnabypa1 is a boolean which states if an LNA bypass switch is used for 5GHz, mid sub-band, chain 1.
# 0 = no LNA bypass swtich (LNA does not have a bypass path)
# 1 = LNA bypass switch is used (LNA has a bypass path)
sb/1/rxgains5gmtrelnabypa1=1

# rxgains5gmtrisoa1 defines the external isolation between Rx and Tx, for 5GHz, mid sub-band, chain 1. Range: 0 - 15
# It is set according to two different equations, depending upon whether the LNA has a bypass path or not:
#   LNA does not have a bypass path: change in RX gain bettwen R and T = (rxgains5gtrisoa1 * 2) + 8, dB
#   LNA does have a bypass path: rxgains5gtrisoa1 = external LNA gain + LNA bypass loss
sb/1/rxgains5gmtrisoa1=5

# rxgains5ghelnagaina1 defines the external LNA gain for 5GHz, high and X1 sub-bands, chain 1. Range: 0 - 7
# actual ext LNA gain = (rxgains5gelnagaina1 * 2) + 6, dB
# LNA gain is 12dB
sb/1/rxgains5ghelnagaina1=3

# rxgains5ghtrelnabypa1 is a boolean which states if an LNA bypass switch is used for 5GHz, high and X1 sub-bands, chain 1.
# 0 = no LNA bypass swtich (LNA does not have a bypass path)
# 1 = LNA bypass switch is used (LNA has a bypass path)
sb/1/rxgains5ghtrelnabypa1=1

# rxgains5ghtrisoa1 defines the external isolation between Rx and Tx, for 5GHz, high and X1 sub-bands, chain 1. Range: 0 - 15
# It is set according to two different equations, depending upon whether the LNA has a bypass path or not:
#   LNA does not have a bypass path: change in RX gain bettwen R and T = (rxgains5gtrisoa1 * 2) + 8, dB
#   LNA does have a bypass path: rxgains5gtrisoa1 = external LNA gain + LNA bypass loss
sb/1/rxgains5ghtrisoa1=5

sb/1/rssi_delta_5gl_c0=3,3,2,2,5,5
sb/1/rssi_delta_5gml_c0=0,2,0,2,3,5
sb/1/rssi_delta_5gmu_c0=0,2,0,2,3,5
sb/1/rssi_delta_5gh_c0=2,5,2,5,5,8
sb/1/rssi_delta_5gl_c1=1,1,2,2,3,3
sb/1/rssi_delta_5gml_c1=-1,1,0,2,1,3
sb/1/rssi_delta_5gmu_c1=-1,1,0,2,1,3
sb/1/rssi_delta_5gh_c1=0,3,2,5,3,6

# 5GHz TX Parameters

# PA parameters for sromrev=11 are defined in a "list" type format to conserve NVRAM space. See below for the list definitions.

# The maxp5gbXa0 parameters are the TX chain 0 maximum TX output power for 5GHz, sub-band X (0-3)
# units of 0.25dB
# max TX power for chain 0, is 0x54=84qdBm=21dBm
sb/1/maxp5ga0=0x54,0x54,0x54,0x54

# The pa5ga0 parameters are the PA parameters for TX chain 0, 5Hz PAs
# The parameter list is in the format of: sub-band0word0, sub-band0word1, sub-band0word2, sub-band1word0, sub-band1word1, sub-band1word2, sub-band2word0, sub-band2word1, sub-band2word2, sub-band3word0, sub-band3word1, sub-band3word2
# These will have to be replaced with values computed from real boards.
# PA parameters for chain 0:
sb/1/pa5ga0=0xFF26,0x176E,0xFD27,0xFF27,0x1795,0xFD23,0xFF25,0x17C8,0xFD1D,0xFF25,0x17D8,0xFD1A

# The pa5gbw4080a0 and a1 parameters are the PA parameters for TX chain 0 and 1, 5Hz PAs
# The parameter list is in the format of: sub-band0word0, sub-band0word1, sub-band0word2, sub-band1word0, sub-band1word1, sub-band1word2, sub-band2word0, sub-band2word1, sub-band2word2, sub-band3word0, sub-band3word1, sub-band3word2
# These will have to be replaced with values computed from real boards.
# PA parameters for chain 0 and chain 1:
sb/1/pa5gbw4080a0=-219,5963,-731,-216,6005,-732,-219,5887,-722,-222,5792,-713

# The maxp5gbXa1 parameters are the TX chain 1 maximum TX output power for 5GHz, sub-band X (0-3)
# units of 0.25dB
# max TX power for chain 1,  is 0x54=84qdBm=21dBm
sb/1/maxp5ga1=0x54,0x54,0x54,0x54

# The pa5ga1 parameters are the PA parameters for TX chain 1, 5Hz PAs
# The parameter list is in the format of: sub-band0word0, sub-band0word1, sub-band0word2, sub-band1word0, sub-band1word1, sub-band1word2, sub-band2word0, sub-band2word1, sub-band2word2, sub-band3word0, sub-band3word1, sub-band3word2
# These will have to be replaced with values computed from real boards.
# PA parameters for chain 1:
sb/1/pa5ga1=0xFF29,0x177C,0xFD29,0xFF29,0x1792,0xFD27,0xFF27,0x17AF,0xFD23,0xFF27,0x17D5,0xFD1E

# The pa5gbw4080a0 and a1 parameters are the PA parameters for TX chain 0 and 1, 5Hz PAs
# The parameter list is in the format of: sub-band0word0, sub-band0word1, sub-band0word2, sub-band1word0, sub-band1word1, sub-band1word2, sub-band2word0, sub-band2word1, sub-band2word2, sub-band3word0, sub-band3word1, sub-band3word2
# These will have to be replaced with values computed from real boards.
# PA parameters for chain 0 and chain 1:
sb/1/pa5gbw4080a1=-215,6064,-739,-220,5934,-728,-217,6007,-732,-220,5914,-724

# Power detector offsets. These parameters are used to offset the measured RF power in 40MHz and 80MHz channels.
# This is needed for some RF front end designs that have a shift in measured power for wider bandwidth channels.
# 20MHz channels are assumed to have zero offset as the PA parameters are usually computed using 20MHz channels.

# pdoffset40ma0, pdoffset40ma1, and pdoffset40ma2 are the offsets for 5GHz, 40MHz channels, for chains 0-2.
# Each number is a 16-bit wide field that is broken up into four 4-bit offsets, one for each sub-band of 0-3.
# Sub-band 3 (X1) is in bits [15:12], sub-band 2 (high) in bits [1sb/1/8], sub-band 1 (mid) in bits [7:4], and sub-band 0 (low) in bits [3:0]
# Each offset is stored in twos compliment format. Units are 1/4 dB.
# Ex: 0x0500 = +1.25dB offset for sub-band 2, that is 1.25dB is added to the measured power to get the correct measured power.
sb/1/pdoffset40ma0=0x2333
sb/1/pdoffset40ma1=0x4444

# pdoffset80ma0, pdoffset80ma1, and pdoffset80ma2 are the offsets for 5GHz, 80MHz channels, for chains 0-2.
# Each number is a 16-bit wide field that is broken up into four 4-bit offsets, one for each sub-band of 0-3.
# Sub-band 3 (X1) is in bits [15:12], sub-band 2 (high) in bits [1sb/1/8], sub-band 1 (mid) in bits [7:4], and sub-band 0 (low) in bits [3:0]
# Each offset is stored in twos compliment format. Units are 1/4 dB.
# Ex: 0x00A0 = -1.5dB offset for sub-band 1, that is 1.5dB is subtraced from the measured power to get the correct measured power.
sb/1/pdoffset80ma0=0x0000
sb/1/pdoffset80ma1=0x1111

# Power-Per-Rate settings:
#
# General notes on these settings:
#   - real_max_power[chain, rate] = max_power[chain] - power_offset[rate]
#
#   - The power offset is in units of 0.5dB.
#       Note: Some offsets are signed offsets. Others are unsigned. Unless explicitly mentioned, offsets should be treated as unsigned.
#
#   - 11n rates mcs8-mcs15, mcs16-mcs23, and mcs24-mcs31 will have the same power-per-rate offsets corresponding to mcs0-mcs7.
#       In other words, the power-per-rate offsets on each chain are irrepsective of the number of streams
#
#   - 11ac rates mcs0-mcs9 will have the same power-per-rate offsets on each chain irrespective of the number of streams
#
#   - mcs32 uses the same power offsets as legacy 40Dup 6 Mbps

# mcsbw205glpo is the 5GHz band, low sub-band, 11a 6-54, 11n mcs0-23, 11ac mcs0-9, 20MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1      0
#                            --- --- --- --- --- --- --- ---------
# Offset for 11a      rates:  -   -   -  54  48  36  24  18,12,9,6
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb0a0/maxp5gb0a1/maxp5b0ga2
sb/1/mcsbw205glpo=0xCA666000

# mcsbw405glpo is the 5GHz band, low sub-band, 11n mcs0-23, 11ac mcs0-9, 40MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb0a0/maxp5gb0a1/maxp5b0ga2
sb/1/mcsbw405glpo=0xCA666000

# mcsbw805glpo is the 5GHz band, low sub-band, 11n mcs0-23, 11ac mcs0-9, 80MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb0a0/maxp5gb0a1/maxp5b0ga2
sb/1/mcsbw805glpo=0xEA666000

# mcsbw1605glpo is the 5GHz band, low sub-band, 11n mcs0-23, 11ac mcs0-9, 160MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb0a0/maxp5gb0a1/maxp5b0ga2
sb/1/mcsbw1605glpo=0

# mcsbw205gmpo is the 5GHz band, mid sub-band, 11a 6-54, 11n mcs0-23, 11ac mcs0-9, 20MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1      0
#                            --- --- --- --- --- --- --- ---------
# Offset for 11a      rates:  -   -   -  54  48  36  24  18,12,9,6
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb1a0/maxp5gb1a1/maxp5b1ga2
sb/1/mcsbw205gmpo=0xCA666000

# mcsbw405gmpo is the 5GHz band, mid sub-band, 11n mcs0-23, 11ac mcs0-9, 40MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb1a0/maxp5gb1a1/maxp5b1ga2
sb/1/mcsbw405gmpo=0xCA666000

# mcsbw805gmpo is the 5GHz band, mid sub-band, 11n mcs0-23, 11ac mcs0-9, 80MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb1a0/maxp5gb1a1/maxp5b1ga2
sb/1/mcsbw805gmpo=0xEA666000

# mcsbw1605gmpo is the 5GHz band, mid sub-band, 11n mcs0-23, 11ac mcs0-9, 160MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb1a0/maxp5gb1a1/maxp5b1ga2
sb/1/mcsbw1605gmpo=0

# mcsbw205ghpo is the 5GHz band, high and X1 sub-bands, 11a 6-54, 11n mcs0-23, 11ac mcs0-9, 20MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1      0
#                            --- --- --- --- --- --- --- ---------
# Offset for 11a      rates:  -   -   -  54  48  36  24  18,12,9,6
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb2a0/maxp5gb2a1/maxp5b2ga2 for high sub-band
# each offset is in half-dB steps of reduction from maxp5gb3a0/maxp5gb3a1/maxp5b3ga2 for X1 sub-band
sb/1/mcsbw205ghpo=0xCA666000

# mcsbw405ghpo is the 5GHz band, high and X1 sub-bands, 11n mcs0-23, 11ac mcs0-9, 40MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb2a0/maxp5gb2a1/maxp5b2ga2 for high sub-band
# each offset is in half-dB steps of reduction from maxp5gb3a0/maxp5gb3a1/maxp5b3ga2 for X1 sub-band
sb/1/mcsbw405ghpo=0xCA666000

# mcsbw805ghpo is the 5GHz band, high and X1 sub-bands, 11n mcs0-23, 11ac mcs0-9, 80MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb2a0/maxp5gb2a1/maxp5b2ga2 for high sub-band
# each offset is in half-dB steps of reduction from maxp5gb3a0/maxp5gb3a1/maxp5b3ga2 for X1 sub-band
sb/1/mcsbw805ghpo=0xEA666000

# mcsbw1605ghpo is the 5GHz band, high and X1 sub-bands, 11n mcs0-23, 11ac mcs0-9, 160MHz BW, power offsets
#                    Nibble:  7   6   5   4   3   2   1    0
#                            --- --- --- --- --- --- --- -----
# Offset for 11n  mcs rates:  -   -   7   6   5   4   3  2,1,0
# Offset for 11ac mcs rates:  9   8   7   6   5   4   3  2,1,0
#
# each offset is in half-dB steps of reduction from maxp5gb2a0/maxp5gb2a1/maxp5b2ga2 for high sub-band
# each offset is in half-dB steps of reduction from maxp5gb3a0/maxp5gb3a1/maxp5b3ga2 for X1 sub-band
sb/1/mcsbw1605ghpo=0

# mcslr5glpo is the 5GHz band, low sub-band, QPSK relative to BPSK rates power offsets
#                    Nibble:  3   2   1    0   rel to
#                            --- --- --- ----- ------
# Offset for 11a      rates:  -   -   -  18,12   9,6
# Offset for 11n  mcs rates:  -   -  2,1  2,1     0
# Offset for 11ac mcs rates: 2,1 2,1 2,1  2,1     0
#                bandwidith: 160 80  40   20
#
# each offset is in half-dB steps of reduction from maxp5gb0a0/maxp5gb0a1/maxp5b0ga2
sb/1/mcslr5glpo=0

# mcslr5gmpo is the 5GHz band, mid sub-band, QPSK relative to BPSK rates power offsets
#                    Nibble:  3   2   1    0   rel to
#                            --- --- --- ----- ------
# Offset for 11a      rates:  -   -   -  18,12   9,6
# Offset for 11n  mcs rates:  -   -  2,1  2,1     0
# Offset for 11ac mcs rates: 2,1 2,1 2,1  2,1     0
#                bandwidith: 160 80  40   20
#
# each offset is in half-dB steps of reduction from maxp5gb1a0/maxp5gb1a1/maxp5b1ga2
sb/1/mcslr5gmpo=0

# mcslr5ghpo is the 5GHz band, high and X1 sub-bands, QPSK relative to BPSK rates power offsets
#                    Nibble:  3   2   1    0   rel to
#                            --- --- --- ----- ------
# Offset for 11a      rates:  -   -   -  18,12   9,6
# Offset for 11n  mcs rates:  -   -  2,1  2,1     0
# Offset for 11ac mcs rates: 2,1 2,1 2,1  2,1     0
#                bandwidith: 160 80  40   20
#
# each offset is in half-dB steps of reduction from maxp5gb2a0/maxp5gb2a1/maxp5b2ga2 for high sub-band
# each offset is in half-dB steps of reduction from maxp5gb3a0/maxp5gb3a1/maxp5b3ga2 for X1 sub-band
sb/1/mcslr5ghpo=0

# sb20in40hrpo is the 20in40 OFDM signed power offsets relative to 20in20 for 64 QAM and above
#                 Nibble:    3    2   1   0
#                         ------ --- --- ---
# Signed offset for band: 5gh/X1 5gl 5gm 2g
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in40hrpo=0

# sb20in80and160hr5glpo is the 5GHz band, low sub-band, 20in80 and 20in160 OFDM signed power offsets for 64 QAM and above
#            Nibble:           3                  2           1      0
#                    -------------------- ---------------- ------- ------
# Signed offset for: 20in80 - 20LLLL/UUUU 20in80 - 20LL/UU 20in160 20in80
#       Relative to:  all other 20in160       20LU/UL      20in20  20in20
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in80and160hr5glpo=0

# sb40and80hr5glpo is the 5GHz band, low sub-band, 40in80 and 40in160 OFDM signed power offsets for 64 QAM and above
#            Nibble:         3            2       1      0
#                    ----------------- ------- ------- ------
# Signed offset for: 40in160 - 40LL/UU 80in160 40in160 40in80
#       Relative to:      40LU/UL      80in80  40in40  40in40
# ------------------------------------------------------------------------------------------------------------
# sb40and80hr5glpo can be a extension ppr for 20/40/80 mcs8/9 but keep the nibble 0
#            Nibble:              3           2           1         0
#                            -----------  ---------  -----------  ------
# Signed offset for band:       2.4G         5GL         5GL       5GL
# Signed offset for:         40/40/20/40  X/X/80/80  40/40/20/20  40in80 
# Offset for 11ac mcs rates:   9/8/9/8     X/X/9/8     9/8/9/8      
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb40and80hr5glpo=0

# sb20in80and160hr5gmpo is the 5GHz band, mid sub-band, 20in80 and 20in160 OFDM signed power offsets for 64 QAM and above
#            Nibble:           3                  2           1      0
#                    -------------------- ---------------- ------- ------
# Signed offset for: 20in80 - 20LLLL/UUUU 20in80 - 20LL/UU 20in160 20in80
#       Relative to:  all other 20in160       20LU/UL      20in20  20in20
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in80and160hr5gmpo=0

# sb40and80hr5gmpo is the 5GHz band, mid sub-band, 40in80 and 40in160 OFDM signed power offsets for 64 QAM and above
#            Nibble:         3            2       1      0
#                    ----------------- ------- ------- ------
# Signed offset for: 40in160 - 40LL/UU 80in160 40in160 40in80
#       Relative to:      40LU/UL      80in80  40in40  40in40
# ------------------------------------------------------------------------------------------------------------
# sb40and80hr5gmpo can be a extension ppr for 20/40/80 mcs8/9 but keep the nibble 0
#            Nibble:              3           2           1         0
#                            -----------  ---------  -----------  ------
# Signed offset for band:         X          5GM         5GM       5GM
# Signed offset for:              X       X/X/80/80  40/40/20/20  40in80 
# Offset for 11ac mcs rates:      X        X/X/9/8     9/8/9/8      
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb40and80hr5gmpo=0

# sb20in80and160hr5ghpo is the 5GHz band, high and X1 sub-bands, 20in80 and 20in160 OFDM signed power offsets for 64 QAM and above
#            Nibble:           3                  2           1      0
#                    -------------------- ---------------- ------- ------
# Signed offset for: 20in80 - 20LLLL/UUUU 20in80 - 20LL/UU 20in160 20in80
#       Relative to:  all other 20in160       20LU/UL      20in20  20in20
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in80and160hr5ghpo=0

# sb40and80hr5ghpo is the 5GHz band, high and X1 sub-bands, 40in80 and 40in160 OFDM signed power offsets for 64 QAM and above
#            Nibble:         3            2       1      0
#                    ----------------- ------- ------- ------
# Signed offset for: 40in160 - 40LL/UU 80in160 40in160 40in80
#       Relative to:      40LU/UL      80in80  40in40  40in40
# ------------------------------------------------------------------------------------------------------------
# sb40and80hr5ghpo can be a extension ppr for 20/40/80 mcs8/9 but keep the nibble 0
#            Nibble:              3           2           1         0
#                            -----------  ---------  -----------  ------
# Signed offset for band:         X        5GH/X1       5GH/X1    5GH/X1
# Signed offset for:              X       X/X/80/80  40/40/20/20  40in80 
# Offset for 11ac mcs rates:      X        X/X/9/8     9/8/9/8      
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb40and80hr5ghpo=0

# sb20in40lrpo is the 20in40 OFDM signed power offsets relative to 20in20 for 16 QAM and below
#                 Nibble:    3    2   1   0
#                         ------ --- --- ---
# Signed offset for band: 5gh/X1 5gl 5gm 2g
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in40lrpo=0

# sb20in80and160lr5glpo is the 5GHz band, low sub-band, 20in80 and 20in160 OFDM signed power offsets for 16 QAM and below
#            Nibble:           3                  2           1      0
#                    -------------------- ---------------- ------- ------
# Signed offset for: 20in80 - 20LLLL/UUUU 20in80 - 20LL/UU 20in160 20in80
#       Relative to:  all other 20in160       20LU/UL      20in20  20in20
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in80and160lr5glpo=0

# sb40and80lr5glpo is the 5GHz band, low sub-band, 40in80 and 40in160 OFDM signed power offsets for 16 QAM and below
#            Nibble:         3            2       1      0
#                    ----------------- ------- ------- ------
# Signed offset for: 40in160 - 40LL/UU 80in160 40in160 40in80
#       Relative to:      40LU/UL      80in80  40in40  40in40
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb40and80lr5glpo=0

# sb20in80and160lr5gmpo is the 5GHz band, mid sub-band, 20in80 and 20in160 OFDM signed power offsets for 16 QAM and below
#            Nibble:           3                  2           1      0
#                    -------------------- ---------------- ------- ------
# Signed offset for: 20in80 - 20LLLL/UUUU 20in80 - 20LL/UU 20in160 20in80
#       Relative to:  all other 20in160       20LU/UL      20in20  20in20
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in80and160lr5gmpo=0

# sb40and80lr5gmpo is the 5GHz band, mid sub-band, 40in80 and 40in160 OFDM signed power offsets for 16 QAM and below
#            Nibble:         3            2       1      0
#                    ----------------- ------- ------- ------
# Signed offset for: 40in160 - 40LL/UU 80in160 40in160 40in80
#       Relative to:      40LU/UL      80in80  40in40  40in40
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb40and80lr5gmpo=0

# sb20in80and160lr5ghpo is the 5GHz band, high and X1 sub-bands, 20in80 and 20in160 OFDM signed power offsets for 16 QAM and below
#            Nibble:           3                  2           1      0
#                    -------------------- ---------------- ------- ------
# Signed offset for: 20in80 - 20LLLL/UUUU 20in80 - 20LL/UU 20in160 20in80
#       Relative to:  all other 20in160       20LU/UL      20in20  20in20
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb20in80and160lr5ghpo=0

# sb40and80lr5ghpo is the 5GHz band, high and X1 sub-bands, 40in80 and 40in160 OFDM signed power offsets for 16 QAM and below
#            Nibble:         3            2       1      0
#                    ----------------- ------- ------- ------
# Signed offset for: 40in160 - 40LL/UU 80in160 40in160 40in80
#       Relative to:      40LU/UL      80in80  40in40  40in40
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/sb40and80lr5ghpo=0

# dot11agduphrpo is the 11g/11a duplicate mode signed power offsets for 64 QAM and above for all of the following:
#   11n/11ac: Dup40, Dup40in80, and Dup40in160 relative to 40in40
#       11ac: Quad80 and Quad80in160 relative to 80in80
#       11ac: Oct160 relative to 160in160
#
#                 Nibble:    3    2   1   0
#                         ------ --- --- ---
# Signed offset for band: 5gh/X1 5gl 5gm 2g
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/dot11agduphrpo=0

# dot11agduplrpo is the 11g/11a duplicate mode signed power offsets for 16 QAM and below for all of the following:
#   11n/11ac: Dup40, Dup40in80, and Dup40in160 relative to 40in40
#       11ac: Quad80 and Quad80in160 relative to 80in80
#       11ac: Oct160 relative to 160in160
#
#                 Nibble:    3    2   1   0
#                         ------ --- --- ---
# Signed offset for band: 5gh/X1 5gl 5gm 2g
#
# each offset is in half-dB steps of signed reduction (i.e. real pwr = maxpwr - signed_offset)
sb/1/dot11agduplrpo=0

# Regulatory parameters
# ccode is the "Country Code". This will be changed depending upon where the board is shipped.
# A value of "ALL" turns off the driver regulatory limits for (Broadcom internal code builds only!)
# and should only be used for testing purposes.
sb/1/ccode=ALL

# regrev is only available in sromrev>=3. It sets a sub-revision of the regulatory locale table for each country code
sb/1/regrev=0

# sar5g is the SAR limit for the 5GHz band
# value is in dBm
# Set 15dBm for 5GHz
# sb/1/sar5g=15


# ledbhX sets the LED behaviour of LEDs connected to the GPIO[3:0] pins of the 4321
# See app note "80211-AN503-R.pdf" for more details.
#  wireless activity - 2 = WL_LED_ACTIVITY
#  2.4GHz radio status - 5 = WL_LED_BRADIO
#  5GHz radio status - 4 = WL_LED_ARADIO
#  not used - 11 = WL_LED_INACTIVE
#
# GPIO 0 is not used - 11 = WL_LED_INACTIVE
sb/1/ledbh0=11
# GPIO 1 is not used - 11 = WL_LED_INACTIVE
sb/1/ledbh1=11
# GPIO 2 is not used - 11 = WL_LED_INACTIVE
sb/1/ledbh2=11
# GPIO 3 is not used - 11 = WL_LED_INACTIVE
sb/1/ledbh3=11

# GPIO 11 is wireless activity - 2 = WL_LED_ACTIVITY
sb/1/ledbh11=0x2

# leddc is the duty cycle for PWM control of the LEDs.
# 0xFFFF sets 100% duty cycle
sb/1/leddc=0xFFFF

# Chip temperature polling period, range 1-14, in units of seconds, 0 means driver decides the value, 15 is reserved
sb/1/temps_period=5
# Temperature threshold above which the chip switches to a single TX chain to prevent damage from overheating
sb/1/tempthresh=120
# Temperature hysteresis, when the chip temperature falls below (tempthresh ?temps_hysteresis), 2-chain TX is re-enabled
# range 1-14, in units of degrees C. 0 means driver decides the value, 15 is reserved
sb/1/temps_hysteresis=5

# Temperature delta, in degrees C, when exceeded will initiate an I/Q calibration. Range 0-63.
sb/1/phycal_tempdelta=0

# Offset to add to tempthresh when boardflag2 bit 24 is set to "1".
sb/1/tempoffset=0


# The following section is to configure the on-board (WOMBO) 43217 chip, 2.4GHz side, when it does not have an SROM.
# These parameters take the place of the SROM contents.
# These parameters must have a special prefix. The format is:
#   'pci/<bus_#>/<slot_#>/<param>'
#
#   where: <bus_#> is the PCI bus number ?always "1" for current chips
#          <slot_#> slot number of the WOMBO chip (i.e. the 43222)
#             slot 0 is the CPU chip (i.e. the 4705)
#             slot = 1 if PCI_AD17 connected to IDSEL pin of the WOMBO chip, or
#                      if the chip is connected to the first PCIe interface
#             slot = 2 if PCI_AD18 connected to IDSEL pin of the WOMBO chip, or
#                      if the chip is connected to the second PCIe interface
#             slot = 3 if PCI_AD19 connected to IDSEL pin of the WOMBO chip, or
#                      if the chip is connected to the third PCIe interface
#          <param> is the parameter assignment. i.e. "boardflags=0xA248"
# Due to the increasing number of NVRAM parameters being added with new wireless chips, sometimes the NVRAM will grow too
# large and not fit in the 4K allocated to it in the CFE image. In order to compress the NVRAM somewhat, the
# "devpathX=<prefix>" notation can be used.
#
# In this notation the "<prefix>" value is the usual prefix as decribed above, like "pci/1/1/".
# The "X" in "devpathX" is a unique number from 0-9. Multiple "devpaths" are supported per NVRAM file. This will be
# needed when a board has multiple wireless chips/interfaces. Suggest to start "X" from 0, and count up.
#
# Then for each prefixed NVRAM parameter, the "X:" part is replaced by <prefix> in the NVRAM parser. This saves space by
# reducing the prefix length from about eight characters ("pci/1/1/") down to two ("1:").
#
# Example:
#   Instead of
#     0:boardflags=0x80001200
#     0:boardflags2=0x00100000
#
#   Use the "devpath" notation:
#     devpath0=0:
#     0:boardflags=0x80001200
#     0:boardflags2=0x00100000
#
devpath0=pci/1/1/

# venid is the "vendor ID" of the wireless chip. 0x14E4 is Broadcom (Epigram)
0:venid=0x14e4

# boardvendor is the same as venid
0:boardvendor=0x14e4

# NOTE: When SROM parameters are used in NVRAM, the "pci/1/1/boardtype", "pci/1/1/boardrev", and "pci/1/1/boardnum"
#       parameters should NOT be placed in NVRAM.

# sromrev tells the software what "version" of SROM is used.
0:sromrev=8

# This is the 'boardflags' parameter for the WOMBO chip only
# boardflags: 32-bits (LSB on top, MSB on bottom)
#   0 = no Bluetooth coexistence                                 1 = 2-wire Bluetooth coex on GPIO 7 & 8
#   0 = GPIO 9 does not control the PA                          (deprecated)
#   0 = does not implement GPIO 13 radio disable (Airline mode)  1 = board implements Airline mode on GPIO 13
#   0 = no RSSI divider                                          1 = has RSSI divider
#         (only applies to older chips like 4712 with an external radio)
#  ---
#   0 = board does not have RoboSwitch or Ethernet switch core   1 = has RoboSwitch chip or Ethernet switch core
#   0 = OK to power down PLL and chip                            (deprecated)
#   0 = no high power CCK (disables opo parameter)               1 = can do high power CCK transmission (enables opo)
#   0 = board does not have ADMtek switch                        1 = board has ADMtek Ethernet switch
#  ---
#   0 = Ethernet switch does not have VLAN capability            1 = Ethernet switch has VLAN capability
#   0 = no Afterburner support                                   1 = board supports Afterburner
#   0 = chip has it's PCI/PCIe interface connected               1 = PCI/PCIe is floating or there is no PCI/PCIe interface on the chip
#   0 = board does not have a FEM                                1 = board uses a FEM
#       (legacy SISO chips only, not used for MIMO chips)
#  ---
#   0 = board does not have an external 2.4GHz LNA               1 = board has an external 2.4GHz LNA
#   0 = board does not have a high gain PA                       1 = board has a high gain PA
#       (legacy SISO chips only, not used for MIMO chips)
#   0 = no alternate Bluetooth coexistence                       1 = 2-wire BT coex on GPIOs 4 & 5
#   0 = do not use alternate IQ imbalance settings               1 = use alt IQ settings
#       (only applies to 4318)
#  ---
#   0 = board has external PA(s)                                 1 = board does not have external PA(s)
#       (legacy SISO chips only, not used for MIMO chips)
#   0 = board's TSSI is negative slope                           1 = board's TSSI is positive slope
#       (legacy SISO chips only, not used for MIMO chips)
#   0 = board does not use the PA voltage reference LDO          1 = board uses the PA voltage reference LDO
#       (only applies to the 4326, 4328, and 5354)
#   0 = no triple-throw switch shared with Bluetooth             1 = has triple-throw switch shared with BT
#  ---
#   0 = board does not support the phase shifter for MRC         1 = board supports the phase shifter for MRC
#       (applies to 4325, 4326, 4328, and 5354 only)
#   0 = board power topology does not use the Buck/Boost reg     1 = board power topology uses the Buck/Boost regulator
#       (4325 only)
#   0 = board does not share antenna with Bluetooth              1 = board has FEM and switch to share antenna with BT
#   0 = board power topology uses CBUCK (core buck)              1 = board power topology does not use CBUCK (core buck)
#       (applies to 4325 only)
#  ---
#   0 = normal CCK EVM and spectral mask                         1 = favor CCK EVM over spectral mask
#   0 = board power topology does not use PALDO                  1 = board power topology use PALDO
#   0 = normal LNLDO2 (low noise LDO2)                           1 = select 2.5V as LNLDO2 (low noise LDO2) output voltage
#       (4325 only)
#   0 = non 4325: no minimum power index                         1 = non 4325: enforce minimum power index to avoid FEM damage
#       (set to "1" only for SiGe SE2559L FEMs)
#       4325: no power-on-reset workaround                           4325: Apply power-on-reset workaround
#  ---
#   0 = board does not have an external 5GHz LNA                 1 = board has an external 5GHz LNA
#   0 = for a 1x2 design, board does not have two T/R switches   1 = for a 1x2 design, board has two T/R switches
#   0 = normal operation of 5GHz T/R switch for high RF          1 = hold T/R switch in the "R" position for high RF input powers.
#       input power.
#   0 = use normal "InitGain"                                    1 = backoff "InitGain" based on the elna2g/5g parameters, for external LNAs only.
#
0:boardflags=0x80001200

# This is the 'boardflags2' parameter for the WOMBO chip only
# boardflags2: 32-bits (LSB on top, MSB on bottom)
#   0 = board uses the 2055's built-in LDOs to power the 2055    1 = board uses external rxbb regulator to power the 2055
#   0 = use normal 5GHz band PLL settings                        1 = use alternate 5GHz band PLL settings
#       (4322x and 4716/17/18 only)
#   0 = do not use H/W TX power control on 4321                  1 = use H/W TX power control on 4321
#       (4321 only)
#   0 = board does not support the 2x4 diversity switch          1 = board supports the 2x4 diversity switch
#  ---
#   0 = board does not support the 5GHz band TX power gain       1 = board supports the 5GHz band TX power gain
#   0 = board does not override the ASPM and CLKREQ settings     1 = board overrides the ASPM and CLKREQ settings
#   0 = board is not a BCM94321mc123 board                       1 = board is a BCM94321mc123 board (unused by S/W)
#   0 = board does not use 3-wire Bluetooth coexistence          1 = board uses 3-wire Bluetooth coexistence
#  ---
#   0 = BCM94321mcm93 uses SiGe FEM                              1 = BCM94321mcm93 uses Skyworks FEM
#       (for BCM94321mcm93 and BCM94321coex boards only)
#   0 = no workaround for clock harmonic spurs                   1 = use the workaround for clock-harmonic spurs
#   0 = use normal 2.4GHz band PLL settings                      1 = use alternate 2.4GHz band PLL settings
#       (4322x and 4716/17/18 only)
#   0 = Normal LED drive (full push-pull)                        1 = Drive the LED outputs as open-drain
#       (43224 only)
#  ---
#   0 = enable TX diversity for 11b frames                       1 = Transmit 11b frames only on antenna 0
#   0 = no WAR to reduce/avoid clock harmonic spurs in 2G band   1 = enable WAR to reduce/avoid clock harmonic spurs in 2G band
#   0 = do not transmit 11b frames using all TX cores            1 = transmit 11b frames using all TX cores
#       (TX diversity enabled or not by bit 12)                      (no TX diversity)
#   0 = use normal filter settings for 2.4GHz bandedge channels  1 = use alternate filter settings for 2.4GHz bandedge channels
#       (4716, 4717, 4718, 5357, 5358, and 47186 internal PAs only)
#  ---
#   0 = do not use 200kHz PLL bandwidth for 2G band              1 = use 200kHz PLL bandwidth for 2G band
#   0 = GPAIO pin is not connected to 3.3V                       1 = GPAIO pin is connected to 3.3V
#       (43226 only)
#   0 = for external PAs, use external TSSI for TX IQCAL         1 = use internal envelope detector for TX IQCAL even with external PAs
#       (4322x and 4716/17/18 only)
#   0 = can turn off the buffered crystal output from the radio  1 = keep the buffered crystal output from radio ON
#  ---
#   0 = control 2GHz PAs with the digital PA control signals     1 = control 2GHz PAs with the analog PA VERF LDO outputs
#   0 = control 5GHz PAs with the digital PA control signals     1 = control 5GHz PAs with the analog PA VERF LDO outputs
#   0 = normal external LNA and TR switch controls               1 = For AZW designs, 2GHz gmode_elna_gain conrols the TR switch
#       (4329 only)
#   0 = no antenna sharing with Bluetooth                        1 = share the chain 0 antenna with Bluetooth
#  ---
#   0 = no adjustment to the temperature threshold, "tempthresh" 1 = chip can sustain a higher tempsense threshold
#                                                                    add the value of parameter "tempoffset" to "tempthresh"
#   0 = use standard 4-wire Bluetooth coexistance                1 = use standard 3-wire Bluetooth coexistance only. 4-wire not supported
#
#   (bits 26-31 are unused)
#
0:boardflags2=0x1800

# This parameter will tell the software to hook to the chip's internal d11 wireless core and tell
# it what type of wireless interface this is. NOTE: Old "wl0id" parameter is deprecated.
#
#   wireless interface type  chips                         device ID
#   -----------------------  ----------------------------  ---------
#   Single band 11g          4306, 4309, 4712, 5350, 5351    0x4320
#   Dual band 11a/g          4306, 4309, 4712                0x4324
#   Single band 11a          4306, 4309                      0x4321
#   Single band 11g          4318, 4320, 5352, 5354          0x4318
#   Dual band 11a/g          4318, 4320                      0x4319
#   Single band 11a          4318                            0x431A
#   Single band 11g          4311                            0x4311
#   Dual band 11a/g          4311                            0x4312
#   Single band 11a          4311                            0x4313
#   Dual band 11a/g          4312, 4326, 4328                0x4314
#   Single band 11g          4312, 4326, 4328                0x4315
#   Single band 11a          4312, 4328                      0x4316
#   Dual band 11a/g          4315                            0x4334
#   Single band 11g          4315                            0x4335
#   Single band 11a          4315                            0x4336
#   Dual band 11n            4321                            0x4328
#   2.4GHz only 11n          4321                            0x4329
#   5GHz only 11n            4321                            0x432A
#   Dual band 11n            4322, 4717*, 4718*              0x432B
#   2.4GHz only 11n          4322, 4716*, 4717*, 4718*       0x432C
#   5GHz only 11n            4322, 4717*, 4718*              0x432D
#   Dual band 11n            4331                            0x4331
#   2.4GHz only 11n          4331                            0x4332
#   5GHz only 11n            4331                            0x4333
#   2.4GHz only 11n          43221                           0x4341
#   2.4GHz only 11n          43231                           0x4340
#   Dual band 11n            43222                           0x4350
#   2.4GHz only 11n          43222                           0x4351
#   5GHz only 11n            43222                           0x4352
#   Dual band 11n            43224                           0x4353
#   2.4GHz only 11n          43224                           0x4354
#   5GHz only 11n            43224                           0x4355
#   2.4GHz only 11n          43225                           0x4357
#   Dual band 11n            43236                           0x4346
#   2.4GHz only 11n          43236/5357/5358/47186           0x4347
#   5GHz only 11n            43236                           0x4348
#
# *NOTE: For 4716/17/18 router chips use a 4321 type ID to avoid a problem if a 4322 type ID is used.
#
# Set the WOMBO chip to be a 2.4GHz only, 11n, 43217 device. It will come up as device eth1, a.k.a wl0
0:devid=0x43a9

# frequency of the 43217's crystal, in kHz
0:xtalfreq=20000

##bcm943217hmitr4l_ssid
#0:boardtype=0x5e9

# 802.11n parameters
# pci/1/1/macaddr sets the MAC address of the WOMBO 11n wireless interface.  See notes above for et0macaddr for the new macmid definition.
#   Reference Board   macmid        Reference Board   macmid         Reference Board     macmid
#   ---------------  ---------      ---------------  ---------       -----------------  ---------
#    BCM94318mpg       4C:6D         BCM94322mp2       4C:D7          BCM943222mpgepa     4C:50
#    BCM94318mpagh     4C:6E         BCM94323usb       4C:D8          BCM943236u          4C:52
#    BCM94318sd        4C:6F         BCM94312mcgb      4C:D9          BCM943236uepa       4C:53
#    BCM94311mcg       4C:8F         BCM94321mcg4      4C:DB          BCM94313hmgbepa     4C:5B
#    BCM94318mpgh      4C:8D         BCM94321mcg4      4C:DC          BCM943236uepa       4C:5C
#    BCM94311mcg       4C:8F         BCM94321hmg       4C:DE          BCM94313hmg21       4C:64
#    BCM94311mcag      4C:90         BCM94322hm        4C:E1          BCM94313hms         4C:65
#    BCM94318cb        4C:95         BCM94322hm2       4C:E2          BCM94313hmb         4C:66
#    BCM94318pc        4C:95         BCM94312mcgsg     4C:E6          BCM94315usbgdl      4C:78
#    BCM94321mp        4C:98         BCM94322mp2d      4C:EC          BCM94331mc          00:3
#    BCM94321cb        4C:99         BCM94322usa       4C:ED          BCM94331mci         00:4
#    BCM94321mc        4C:9A         BCM94322usab      4C:EE          BCM94331pcibt4      00:5
#    BCM94321xc        4C:9B         BCM94315usbgp     4C:FE          BCM943223mp         00:E
#    BCM94318mpaghl    4C:A2         BCM94315usbgp4l   4C:02          BCM95357nr(5GHz)    02:1
#    BCM94318mpgsg     4C:A3         BCM94323usb2d     4C:0C          BCM95357nrepa(5GHz) 02:2
#    BCM94318mpgsy     4C:A4         BCM94323usb2f     4C:0D          BCM947186nrh(5GHz)  02:4
#    BCM94318mpgshlr   4C:AF         BCM943221mc2      4C:17          BCM94331pciebt12    03:1
#    BCM94328ug        4C:B3         BCM943222mp       4C:19          BCM943236usb        03:2
#    BCM94328uag       4C:B4         BCM943222mpf      4C:1A          BCM94331hm          03:4
#    BCM94328pc        4C:B5         BCM943222mp2      4C:1B          BCM943227hm4l       04:1
#    BCM94328cf        4C:B6         BCM943231usb2Gipa 4C:1C          BCM943227hmb        04:2
#    BCM94312mcg       4C:BB         BCM943224hm       4C:1E          BCM943228hm4l       04:3
#    BCM94312mcag      4C:BD         BCM943224hms      4C:1F          BCM943236usbepa     04:8
#    BCM94326usbgp     4C:C2         BCM943231usb2G_1x2 4C:20         BCM943236ue         04:9
#    BCM94321mc123     4C:C8         BCM943225hm2      4C:21          BCM943224pciebt2    05:1
#    BCM94328uagk      4C:CA         BCM943225hm2b     4C:22          BCM943238ucg        05:2
#    BCM94326ugtDu     4C:CD         BCM94321coex2ref  4C:25          BCM943235u          05:3
#    BCM94328csp       4C:CE         BCM943221hm2      4C:26          BCM943227hm2l       05:B
#    BCM94321mp3c2     4C:CF         BCM94312hmgb      4C:2B          BCM943227hmepa2l    05:C
#    BCM94326usbgpj    4C:D0         BCM943224hmb      4C:2C          BCM943228hmb        05:E
#    BCM94321m93       4C:D1         BCM943224mx16     4C:38          BCM943228hmb3c      05:F
#    BCM94322mc        4C:D4         BCM943224hmx      4C:39          BCM94706nhr(2.4GHz) 0B:5
#    BCM94322mcres     4C:D5         BCM943111mp2      4C:4B          BCM94706nhr(5GHz)   0B:6
#    BCM94322mp        4C:D6         BCM943112mp2      4C:4D          BCM94707nr(2.4GHz)  0F:C
#                                                                     BCM94707nr(5GHz)    0F:D
#																																			BCM94708acnr(2.4GHz)  14:1
#                                                                     BCM94708acnr(5GHz)    14:2
# New style:
# The value of 00:90:4C:1E:4 is for a BCM947189acnrm reference design (2.4GHz side).
0:macaddr=00:90:4C:1E:4${maclo12}

#Units of 0.25 dB. OFDM power offset. pa0maxpwr - opo = max OFDM tx power (in qdbm) for this board.
0:opo=68

# pci/1/1/aa2g sets which antennas are available for 2.4GHz. Value is a bit field:
# Bit 0 = 1 for antenna 0 is available, 0 for not.
# Bit 1 = 1 for antenna 1 is available, 0 for not.
# Bit 2 = 1 for antenna 2 is available, 0 for not.
# Bit 3 = 1 for antenna 3 is available, 0 for not.
# the 43217 chip has two 2.4GHz antennas available
0:aa2g=0x3

# agX sets the antenna gain for antenna X. Lower 6 bits are interpreted as a signed number representing
# whole dB. Hi 2 bits represent number of quarter dBs. qdB's are ALWAYS POSITIVE and are
# added to whole dBs, so -1 whole dB and 1 qdB = 0x7F = -1dB + 0.25dB = -0.75dB. Range is
# -32dB to +31.75 dB.
# set 0dB gain for all available antennas
0:ag0=0x2
0:ag1=0x2
0:ag2=0xff
0:ag3=0xff

# 2.4G boardswitcharch, rssiav, rssimc & rssimf 
0:bxa2g=0x0
0:rssisav2g=0x0
0:rssismc2g=0x0
0:rssismf2g=0x0

0:tri2g=0x0

# RX power offset for 2.4Ghz
0:rxpo2g=0x0

# txchain is a bit field that sets how many TX chains are implemented.
# Bit 0 = 1 for TX chain 0 is implemented, 0 for not.
# Bit 1 = 1 for TX chain 1 is implemented, 0 for not.
# Bit 2 = 1 for TX chain 2 is implemented, 0 for not.
# Bit 3 = 1 for TX chain 3 is implemented, 0 for not.
# 43217 has TX chains 0 and 1
0:txchain=0x3

# rxchain is a bit field that sets how many RX chains are implemented.
# Bit 0 = 1 for RX chain 0 is implemented, 0 for not.
# Bit 1 = 1 for RX chain 1 is implemented, 0 for not.
# Bit 2 = 1 for RX chain 2 is implemented, 0 for not.
# Bit 3 = 1 for RX chain 3 is implemented, 0 for not.
# 43217 has RX chains 0 and 1
0:rxchain=0x3

# antswitch sets the type of antenna diversity switch used on the board
# 0 = no antenna diversity switch, not 2-of-3
# 1 = antenna diversity switch config as on BCM94321cb2 2of3
# 2 = antenna diversity switch config as on BCM94321mp 2of3
# 3 = antenna diversity switch config as on any 2of3 design newer than 4321
0:antswitch=0x0

# tssipos2g sets the slope for the 2.4GHz TSSI to be either 0=negative or 1=positive
# set positive slope
0:tssipos2g=0x1

# extpagain2g sets what type of external 2.4GHz PA is used: 0 = full gain PA,  1 = PA "lite",  2 = no external PA, 3 = high power external PA
0:extpagain2g=0x0

# pdetrange2g is an index into a table that selects one of 32 possible voltage ranges for the TSSI power detector
# inputs from the PA/FEM for the 2.4GHz band. Defined ranges are:
#
# For: 4331
#               TSSI voltage
# pdetrange2g    min     max   Notes
# -----------  ------  ------  -------------------------------------
#      4       0.252V  1.092V  for Eiffel dual-band FEM (SiGe SE5503A)
#      5       0.193V  0.793V  for descrete PA on Ant1
#              0.252V  1.092V  and Eiffel dual-band FEM (SiGe SE5503A) on Ant0 & Ant2
#      6                       not defined for the 2.4GHz band
#      7                       not defined for the 2.4GHz band
#
# Consult H/W Apps for creation of any new ranges.
#
# set the standard range for most PAs and FEMs TBD
0:pdetrange2g=0x3

# antswctl2g is a number that selects what RF switch architecture (1 of 32) is used on the board for the 2.4GHz band
# 4321 through 43224 and 4716/17/18: 0 = 2-of-3 design. 2 = 2x2 design. All other values reserved.
# 5357/5358/47186: 0 = invalid. 1 = 2x2 design with SPDT switches or 2-of-3 design with diamond switches. 3 = 2-of-3 with five SPDT switches
# 43236: 0 = 2x2 design with SPDT switches or a 2-of-3 design with two diamond switches and one SPDT switch
# 4331: 0 = default, all others reserved

# triso2g is a number, 0-7, that sets the T/R switch isolation for the 2.4GHz band according to the following table:
#
#                           T/R switch isolation for given triso2g value
# Chip                       0     1     2     3     4     5     6     7
# -----------------------  ----  ----  ----  ----  ----  ----  ----  ----
# 4322/4716/4717/4718       3dB   7dB  12dB  15dB  20dB  24dB  28dB  32dB
# 43221/43222/43224/43225  12dB  16dB  20dB  24dB  28dB  32dB  36dB  40dB
#
# For most designs this is set to the mid-point of "3". If the T/R switch isolation on a given design is not
# "typical" then this number might have to be adjusted up or down.
0:triso2g=0x4
#0:triso5g=0

# set the default antenna switch controls
0:antswctl2g=0x0

# elan2g is used to backoff the "InitGain" of the 2.4GHz receivers to compensate for the gain provided by the external LNA.
# This backoff will only be applied if bit 31 of "pci/2/1/boardflags" is set to "1".
# For the 4322, 4716, 4717, 4718, 43222, 43224, and 42225:
#   The amount of backoff is equal to elna2g * 3dB + 6dB. So elna2g=0 sets 6dB of backoff, elna2g=1 sets 9dB of backoff, etc...
# For the 43236, 5357, 5358U, 5358, and 47186:
#   The amount of backoff is equal to elna2g * 3dB + 9dB. So elna2g=0 sets 9dB of backoff, elna2g=1 sets 12dB of backoff, etc...
# For the 4331:
#   The amount of backoff is equal to elna2g * 2dB + 8dB. So elna2g=0 sets 8dB of backoff, elna2g=1 sets 10dB of backoff, etc...
# Set 12dB of backoff for the 2.4GHz LNA
0:elna2g=0x2

# maxp2ga0 is the TX chain 0 maximum TX output power for 2.4GHz
# units of 0.25dB
# max TX power is 0x54=84qdBm=21dBm
0:maxp2ga0=0x54

# itt2ga0 is the TX chain 0 idle target TSSI value for 2.4GHz
0:itt2ga0=0x20

# The following three parameters are the PA parameters for the TX chain 0, 2.4GHz, PA
0:pa2gw0a0=0xfed5
0:pa2gw1a0=0x1965
0:pa2gw2a0=0xfac2

# maxp2ga1 is the TX chain 1 maximum TX output power for 2.4GHz
# units of 0.25dB
# max TX power is 0x54=84qdBm=21dBm
0:maxp2ga1=0x54

# itt2ga1 is the TX chain 1 idle target TSSI value for 2.4GHz
0:itt2ga1=0x20

# The following three parameters are the PA parameters for the TX chain 1, 2.4GHz, PA
0:pa2gw0a1=0xff02
0:pa2gw1a1=0x1b8b
0:pa2gw2a1=0xfaae

# Power per rate settings from TXPER run on two P200 boards and ACPR tests run on one P200 board, from 1/12/2011 - 1/25/2011.
#
#                     Limit From
#                  TXPER  ACPR  TSSI
#                  -----  ----  ----
# Max Power (dBm)    30    30    30   (same for A0 and A1)
#
#                   A0 Limit From:                          A1 Limit From:
#               20MHz              40MHz                20MHz              40MHz
# Rate    TXPER  ACPR  Reg.  TXPER  ACPR  Reg.    TXPER  ACPR  Reg.  TXPER  ACPR  Reg.
# ----    -----  ----  ----  -----  ----  ----    -----  ----  ----  -----  ----  ----
#   1      30     30   TBD    n/a    n/a  n/a      30     30   TBD    n/a    n/a  n/a
#  11      30     29   TBD    n/a    n/a  n/a      30     29   TBD    n/a    n/a  n/a
# mcs0     30     29   TBD    30     27.5 TBD      30    28.5  TBD    30    27.5  TBD
# mcs1     30     29   TBD    30     27.5 TBD      30    28.5  TBD    30    27.5  TBD
# mcs2     30     29   TBD    30     27.5 TBD      30    28.5  TBD    30    27.5  TBD
# mcs3     30     29   TBD    30     27.5 TBD      30    28.5  TBD    30    27.5  TBD
# mcs4     30     29   TBD    30     27.5 TBD      30    28.5  TBD    30    27.5  TBD
# mcs5     25.5   29   TBD    26.5   27.5 TBD      25.5  28.5  TBD    26.5  27.5  TBD
# mcs6     24.5   29   TBD    26     27.5 TBD      24.5  28.5  TBD    25.5  27.5  TBD
# mcs7     23.5   29   TBD    25     27.5 TBD      23.5  28.5  TBD    25    27.5  TBD

# cck2gpo is the 2.4GHz band 11b CCK power offsets
#          Nibble:  3   2   1   0
#                  --- --- --- ---
# Offset for rate: 11  5.5  2   1
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/cck2gpo=0x2200
0:cck2gpo=0x0

# ofdm2gpo is the 2.4GHz band, legacy 11g and 11n mcs0-7 SISO, 20MHz BW, OFDM power offsets
#              Nibble:  7   6   5   4   3   2   1   0
#                      --- --- --- --- --- --- --- ---
# Offset for 11g rate: 54  48  36  24  18  12   9   6
# Offset for mcs rate: 7,6  5   4   3   2   1   -   0
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/ofdm2gpo=0xD9333333
0:ofdm2gpo=0x44222000

# mcs2gpo0 is the 2.4GHz band, legacy 11g and 11n mcs0-3, CDD, 20MHz BW, power offsets
# For the 5356, this is the 2.4GHz, 11n mcs0-3, SSN, 20MHz BW, power offsets.
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for 11g rate:  24  18  12 9,6
# Offset for mcs rate:   3   2   1   0
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo0=0x3333
0:mcs2gpo0=0x2000

# mcs2gpo1 is the 2.4GHz band, legacy 11g and 11n mcs4-7 CDD, 20MHz BW, power offsets
# For the 5356, this is the 2.4GHz, 11n mcs4-7, SSN, 20MHz BW, power offsets.
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for 11g rate:   -  54  48  36
# Offset for mcs rate:   7   6   5   4
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo1=0xDB93
0:mcs2gpo1=0x4422

# mcs2gpo2 is the 2.4GHz band, 11n mcs8-11 SDM, 20MHz BW, power offsets
# For the 5356, this is the 2.4GHz, 11n mcs0-3, SSN, 40MHz BW, power offsets.
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for mcs rate: 11  10   9   8
# Offset for 5356, mcs: 3   2   1   0
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo2=0x3333
0:mcs2gpo2=0x2000

# mcs2gpo3 is the 2.4GHz band, 11n mcs12-15 SDM, 20MHz BW, power offsets
# For the 5356, this is the 2.4GHz, 11n mcs4-7, SSN, 40MHz BW, power offsets.
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for mcs rate: 15  14  13  12
# Offset for 5356, mcs: 7   6   5   4
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo3=0xDB93
0:mcs2gpo3=0x4422

# mcs2gpo4 is the 2.4GHz band, legacy 11g and 11n mcs0-3, CDD, 40MHz BW, power offsets
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for 11g rate:  24  18  12 9,6
# Offset for mcs rate:   3   2   1   0
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo4=0x5555
0:mcs2gpo4=0x2000

# mcs2gpo5 is the 2.4GHz band, legacy 11g and 11n mcs4-7 CDD, 40MHz BW, power offsets
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for 11g rate:   -  54  48  36
# Offset for mcs rate:   7   6   5   4
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo5=0xA975
0:mcs2gpo5=0x4422

# mcs2gpo6 is the 2.4GHz band, 11n mcs8-11 SDM, 40MHz BW, power offsets
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for mcs rate: 11  10   9   8
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo6=0x5555
0:mcs2gpo6=0x2000

# mcs2gpo7 is the 2.4GHz band, 11n mcs12-15 SDM, 40MHz BW, power offsets
#              Nibble:  3   2   1   0
#                      --- --- --- ---
# Offset for mcs rate: 15  14  13  12
#
# each offset is in half-dB steps of reduction from maxp2ga0/maxp2ga1
#sb/1/mcs2gpo7=0xA975
0:mcs2gpo7=0x4422

# cddpo is the CDD power offset (will be added to the offset from mcs[2g,5g,5gl,5gh]po[0,1,4,5] to obtain the net CDD power offset)
#          Nibble:  3   2   1   0
#                  --- --- --- ---
# Offset for band: 5gh 5gl 5gm  2g
#
# each offset is in half-dB steps of reduction
#sb/1/cddpo=0x0000
0:cddpo=0x0

# stbcpo is the STBC power offset (will be added to the offset from mcs[2g,5g,5gl,5gh]po[0,1,4,5] to obtain the net STBC power offset)
#          Nibble:  3   2   1   0
#                  --- --- --- ---
# Offset for band: 5gh 5gl 5gm  2g
#
# each offset is in half-dB steps of reduction
#sb/1/stbcpo=0x0000
0:stbcpo=0x0

# bw40po is the Additional 40 MHz OFDM power-offset across legacy 11g and mcs0-15 11n rates
# It will be added to either the ofdm[2g,5g,5gl,5gh]po or mcs[2g,5g,5gl,5gh]po[4-7] offsets in addition to the CDD or STBC power-offsets (if applicable)
# to get the total offset.
#          Nibble:  3   2   1   0
#                  --- --- --- ---
# Offset for band: 5gh 5gl 5gm  2g
#
# each offset is in half-dB steps of reduction from the 20MHz OFDM power (not board max power)
#sb/1/bw40po=0x0000
0:bw40po=0x0

# bwduppo is the "duplicate 20MHz in 40MHz BW" power offsets, with regard to 20MHz offsets
#          Nibble:  3   2   1   0
#                  --- --- --- ---
# Offset for band: 5gh 5gl 5gm  2g
#
# each offset is in half-dB steps of reduction
# NOTE: This parameter is not yet supported and should be set to zero.
#sb/1/bwduppo=0
0:bwduppo=0x0

# Regulatory parameters
# ccode is the "Country Code". This will be changed depending upon where the board is shipped.
# A value of "0" turns off the driver regulatory limits and should only be used for testing purposes.
#sb/1/ccode=0
0:ccode=#a

# regrev is only available in sromrev>=3. It sets a sub-revision of the regulatory locale table for each country code
#sb/1/regrev=0
0:regrev=0

# ledbhX sets the LED behaviour of LEDs connected to the GPIO[3:0] pins of the 4321
# See app note "80211-AN503-R.pdf" for more details.
# GPIO 0 is not used - 11 = WL_LED_INACTIVE
0:ledbh0=11
# GPIO 1 is not used - 11 = WL_LED_INACTIVE
0:ledbh1=11
# GPIO 2 is not used - 11 = WL_LED_INACTIVE
0:ledbh2=11

# GPIO 3 is wireless activity - 2 = WL_LED_ACTIVITY
# Driver can actually control more LEDs.
0:ledbh3=2

# leddc is the duty cycle for PWM control of the LEDs.
# 0xFFFF sets 100% duty cycle
0:leddc=0xFFFF

# Chip temperature polling period, range 1-14, in units of seconds, 0 means driver decides the value, 15 is reserved
0:temps_period=5

# Temperature threshold above which the chip switches to a single TX chain to prevent damage from overheating
0:tempthresh=120

# Temperature hysteresis, when the chip temperature falls below (tempthresh ?temps_hysteresis), 2-chain TX is re-enabled
# range 1-14, in units of degrees C. 0 means driver decides the value, 15 is reserved
0:temps_hysteresis=5

# Temperature delta, in degrees C, when exceeded will initiate an I/Q calibration. Range 0-63.
0:phycal_tempdelta=0

# Offset to add to tempthresh when boardflag2 bit 24 is set to "1".
0:tempoffset=0
